`timescale 1ns/1ps
module circuit1_top ;
	reg clk,a,b,c,n_clr;
	always # 1 clk = ~clk;
	initial begin
		clk = 0;
		n_clr = 0;
		a = 0;
		b = 0;
		c = 0;
		# 3 n_clr = 1 ;
		# 3 
		a=1;b=0;c=0;
		# 2	a=1;b=0;c=0;
		# 2 a=0;b=1;c=0;
		# 2 a=1;b=1;c=0;
		# 2	a=0;b=0;c=1;
		# 2	a=0;b=0;c=1;
		# 2	a=1;b=0;c=1;
		# 2	a=0;b=1;c=1;
		# 2	a=1;b=1;c=1;
		# 2 n_clr = 0;
		# 2 $finish;
	end
	circuit1 c1(dout,a,b,c,clk,n_clr);
initial
  	begin
    	$dumpfile("test.vcd");
    	$dumpvars(0, c1);
  	end 
endmodule
module circuit1(dout,a,b,c,clk,n_clr);
	input a,b,c,clk,n_clr;
    output reg dout;
    wire t1,t2,t3;
    assign t1 = ~(a&b);
    assign t2 = ~c;
    assign t3 = t1 | t2;
    always @(posedge clk)
        if(!n_clr)
            dout <= 0;
    	else
            dout <= t3;
endmodule
